A high-speed method of dynamic comparators for SAR analog to digital converters

A low-power high-speed two-stage dynamic comparator is presented. The voltage fluctuation at the first stage of the comparator (pre-amplifier stage) is limited to Vdd/2. Therefore, the power consumption of the first stage which is the dominant part of the total power consumption is reduced. The output voltage of the first stage is kept above Vdd/2. As a result, during the comparison the second stage of the comparator (latch) is activated stronger compared to the conventional comparator. To prove the benefits of the proposed comparator, the proposed and the other circuits are simulated in the equal budget of power and offset. Simulation results prove that the proposed comparator is faster by a factor of two. The comparator delay, dynamic offset, and power consumption (at 500 MHz) are 255 ps, 2.6 mV, and 420 uW respectively. Moreover, the maximum input common mode of the proposed circuit is 94%Vdd at 500MHz which is better than the conventional method (68%Vdd).